A Tesla accelerator roadmap reported by Tom's Hardware gives the company's chips Super Intelligence labels, promises an 80-fold performance increase and brings its previously abandoned Dojo program back into focus. The company's next-generation SI6 inference processor is scheduled for 2029–2030, while its redesigned Dojo 3 training hardware is being developed with potential space deployments in mind.
The roadmap, on a slide Tom's Hardware itself calls an "alleged Tesla slide", shows the existing AI4, AI5 and AI6 designations as SI4, SI5 and SI6. Tom's Hardware treats this as a rename, but the report cites no separate Tesla statement about the name. Behind the labels, however, are substantial changes to chip architecture, manufacturing plans and memory technology.
SI labels on the roadmap
The slide replaces the familiar AI labels across its accelerator generations. The company's fourth-generation inference processor, previously known as HW4 and subsequently AI4, now appears as SI4. Its forthcoming fifth- and sixth-generation products similarly carry the SI5 and SI6 names.
Tom's Hardware also says Musk recently confirmed that SpaceXAI, the artificial intelligence venture associated with SpaceX, would be redubbed SpaceXSI.
The article embeds a November 4 post on X that spotted the new labels and linked them to President Donald Trump's preference for replacing the conventional AI terminology with Super Intelligence, saying Musk "may already be embracing" it. That link is the poster's guess.
The labels do not themselves establish that Tesla has developed a new class of intelligence. The roadmap concerns computing hardware designed for inference and training workloads. Those are different technical functions, and the SI designation should not be mistaken for evidence that the chips independently achieve superintelligence.
For Tesla, the more consequential development is the hardware underneath the new names. The roadmap outlines increasingly powerful inference processors, more sophisticated packaging and a separate training accelerator that could operate beyond conventional terrestrial data centers.
Dojo returns in new form
The most unexpected part of the announcement concerns Dojo 3, Tesla's next-generation training accelerator. The project has a complicated history: Musk cancelled the original wafer-scale Dojo effort in August 2025, and in August 2026 said SpaceX and xAI would rely exclusively on Nvidia hardware for their terrestrial and extraterrestrial data centers.
The new presentation nevertheless brings Dojo back into Tesla's plans. Its third generation will not simply repeat the designs of Dojo D1 and D2. Instead, Tesla describes a chiplet-based architecture combining two-and-a-half-dimensional and three-dimensional packaging with stacked high-bandwidth memory.
That is a significant departure from the original approach. The first Dojo generation used a system-on-wafer design, placing interconnected processors across a large silicon structure. Its architecture relied heavily on static random-access memory, or SRAM, distributed across the processing hardware.
The original D1 configuration connected 25 processors and provided a combined 11 GB of SRAM. This arrangement allowed processing elements to access nearby memory without relying entirely on separate memory packages. It was a specialized design intended to support demanding AI training workloads.
Dojo 3's proposed use of high-bandwidth memory (HBM) points toward a different balance between computing capacity and memory. Modern AI models require substantial storage for model parameters, intermediate calculations and activations. SRAM can deliver fast access, but its limited density makes it expensive and difficult to scale to the capacities required by increasingly large models.
Why Dojo needs chiplets
Moving toward HBM could help Tesla increase memory capacity without relying exclusively on enormous quantities of on-chip SRAM. But the change also introduces engineering compromises. HBM requires advanced packaging, and stacking memory close to processing dies makes thermal management more complicated.
Tesla has not clarified whether Dojo 3 will abandon wafer-scale integration entirely. One possible configuration would combine HBM stacks with logic dies connected through wafer-scale packaging. That would preserve some of the original architecture while introducing a different memory subsystem.
Such a design would be technically demanding. Combining wafer-scale interconnects with stacked memory would increase manufacturing complexity, complicate cooling and create additional reliability considerations. The resulting package could also become more expensive to produce.
Manufacturing yields are another concern. Large integrated structures can be difficult to manufacture consistently, and introducing additional stacked components creates more opportunities for defects. Designers can mitigate some problems through redundancy and improvements in manufacturing processes, but those measures add costs of their own.
For these reasons, Tom's Hardware considers a more conventional chiplet arrangement a plausible direction for D3. Rather than attempting to reproduce the original wafer-scale approach, Tesla may prioritize a modular architecture that is easier to manufacture and expand.
The presentation does not settle the question. Tesla has not released the accelerator's processing performance, memory capacity, manufacturing node or expected availability date. The company has therefore revealed its architectural direction without providing enough information to establish how competitive the finished product will be.
Dojo 3 targets space
Tesla describes D3 as being designed around three priorities: space, training and scalability. The reference to space is particularly notable because it indicates that the company is considering environments beyond conventional computing facilities.
Extraterrestrial operation would impose additional requirements on electronic hardware. Radiation exposure, for example, can interfere with semiconductor operation and damage electronic components. Hardware intended for space applications may therefore need radiation-resistant designs or other protective measures.
Tom's Hardware suggests that at least some Dojo 3 configurations could incorporate radiation hardening. Tesla has not confirmed the exact measures, however, and the presentation does not establish which components or versions would receive such treatment.
The space requirement also adds another dimension to the packaging question. High-performance processors already generate substantial heat, while advanced memory stacks create additional thermal-management challenges. Designing a system that can operate reliably in a demanding environment could require compromises between computing density, cooling and power consumption.
The company's emphasis on scalability may help explain the move toward chiplets. Modular processors can potentially be combined into larger computing systems without requiring every component to occupy one enormous silicon structure. That approach could offer greater flexibility as training requirements grow.
However, Tesla has not explained how D3 would be deployed, whether it would replace Nvidia-based systems in any existing plans, or how the accelerator would fit into SpaceX's previously stated hardware strategy. Its reappearance establishes that Tesla is again pursuing an in-house training processor, not that the earlier commitment to Nvidia has been reversed across every project.
SI6 promises 80-fold gains
The inference side of Tesla's roadmap offers more concrete performance targets. Its sixth-generation accelerator, SI6, is expected to deliver 80 times the computing performance of the current HW4 baseline. The presentation also indicates a substantial increase in memory capacity.
According to the estimates discussed by Tom's Hardware, the target could correspond to approximately 17,280–46,080 TOPS, or 17.28–46.08 quadrillion operations per second. TOPS means trillion operations per second, a commonly used measurement for the processing throughput of AI accelerators.
The wide range reflects an important uncertainty: Tesla has not officially published the absolute performance of HW4. Musk previously said the fourth-generation processor was between three and eight times more powerful than HW3, whose published rating was 72 TOPS. Applying that estimated range produces different possible starting points for calculating SI6 performance.
Consequently, the projected SI6 figures should be treated as estimates rather than confirmed specifications. The presentation also does not identify which numerical formats the new processor will support. That information matters because accelerator performance can vary substantially depending on whether calculations use lower-precision or higher-precision data formats.
Memory capacity is another major part of the improvement. The roadmap indicates that SI6 will have nine times the memory of HW4, translating to approximately 144 GB under the assumptions used in the analysis. That would give the processor substantially more room for model data and other information needed during inference.
For comparison, Nvidia's Rubin GPU is listed with 50 PFLOPS of NVFP4 inference performance, 35 PFLOPS of NVFP4 training performance and 17.5 PFLOPS using FP8 or FP6 formats. PFLOPS measures quadrillions of floating-point operations per second, but comparisons with TOPS require care because the numerical formats and workloads may differ.
There is also a major timing distinction. Nvidia's Rubin hardware is already shipping to customers, while Tesla's SI6 is not expected until 2029–2030. Even if the projected performance targets are achieved, the comparison involves products separated by several years of development and potentially different measurement methods.
Samsung secures SI6 production
Tesla has already reached an agreement with Samsung Foundry to manufacture its sixth-generation inference accelerators through 2033. The new roadmap identifies a 2nm-class manufacturing process for SI6.
The precise manufacturing technology remains unspecified. Tom's Hardware points to several possible candidates within Samsung's roadmap, including automotive-oriented SF2A, performance-focused SF2P and SF2Z, which incorporates backside power delivery.
These are potential interpretations rather than confirmed process selections. The planned production period and the chip's expected arrival provide clues, but Tesla has not identified the exact Samsung technology that will be used.
One notable omission is Intel. Despite the broader discussion surrounding Tesla's Terafab manufacturing ambitions and Intel's 14A fabrication technology, the SI6 roadmap does not indicate that the accelerator will be manufactured at Terafab using that process in the 2030s.
The manufacturing decision matters because advanced accelerators depend on more than transistor density. Packaging, power delivery, memory integration and manufacturing yields all influence the final product. Tesla's continued reliance on Samsung for SI6 suggests that the company is maintaining a dedicated external manufacturing arrangement for this generation.
SI5 bridges the generations
Before SI6 arrives, Tesla plans to introduce its fifth-generation inference accelerator, SI5, also known as HW5 or AI5. The roadmap identifies both TSMC and Samsung Foundry as manufacturing partners, with 3nm- and 2nm-class process technologies respectively.
SI5 will also introduce a multi-chip module (MCM) design. Instead of relying on a single conventional processor package, an MCM combines multiple semiconductor dies into one package. This can allow manufacturers to combine processing components and improve overall system capabilities.
Tesla expects SI5 to deliver 40 times the performance of HW4. Musk previously described the improvement as the result of two major factors: an eightfold increase in computing resources and a further fivefold gain through silicon optimization.
Multiplying those improvements produces the stated 40-fold target. Based on the same uncertain HW4 performance baseline, Tom's Hardware estimates that SI5 could reach approximately 8,640–23,040 TOPS.
The fifth-generation chip is also expected to consume between 250W and 800W, depending on its intended application. That wide power range makes early performance comparisons difficult. A processor operating at a substantially higher power level may achieve greater throughput, but efficiency and cooling requirements become increasingly important.
Memory is expected to increase sixfold compared with HW4, reaching approximately 96 GB. The actual bandwidth will depend on whether Tesla selects GDDR6 or GDDR7 memory. The estimates discussed by Tom's Hardware range from 768 GB/s to 1.536 TB/s, reflecting the different possible memory configurations.
HW4 sets the baseline
Understanding Tesla's targets requires examining the fourth-generation processor used in its vehicles today. HW4, labeled SI4 on the roadmap, is the company's current reference point for its Full Self-Driving (FSD) technology, the software system intended to support automated driving functions.
The chip is manufactured by Samsung Foundry using a 7nm-class process and employs conventional flip-chip ball grid array packaging. That packaging method connects the semiconductor die to a substrate through an array of small solder connections.
The processor is also believed to use 16 GB of GDDR6 memory. Tesla has not officially confirmed the complete memory specification, however, and it does not publish the chip's absolute compute performance or power consumption.
Tom's Hardware notes that the roadmap presentation itself appears to contain a manufacturing-node error, labeling HW4 as a 5nm-class product. The publication identifies the actual manufacturing technology as Samsung's 7nm-class process.
Musk has previously characterized HW4 as three to eight times more powerful than HW3. Since HW3 carries an official rating of 72 TOPS, that statement implies a possible HW4 performance range of 216–576 TOPS. These values are calculated estimates, not specifications published by Tesla.
The memory question remains
An important distinction across the roadmap is that Tesla has not announced HBM for its upcoming inference accelerators. SI5 and SI6 both retain the multi-chip module approach, which provides a progression from the packaging strategy being introduced with the fifth generation.
The company may eventually adopt HBM for these processors, but the latest presentation does not establish that it will happen with SI6. Instead, the substantial memory increases currently described for the inference products should not be confused with confirmation of an HBM implementation.
The distinction matters because automotive and other inference applications face different requirements from large-scale model training. Memory capacity, bandwidth, power consumption and packaging costs must be balanced against the specific workloads a processor is expected to handle.
A multi-chip design can also provide a practical route to greater performance without requiring a single, increasingly complex monolithic die. Tesla's experience with SI5 could help inform the design of SI6, potentially allowing the company to retain a familiar packaging approach while improving processing resources and memory capacity.
Other automakers are also considering chiplet-based systems-in-package designs and HBM for future vehicle computing platforms. These technologies could increase the cost of advanced automotive processors, but they also offer manufacturers additional ways to scale computing capabilities.
Tesla's roadmap therefore reflects two related but distinct development paths: increasingly capable inference processors for its existing vehicle and computing ecosystem, and a redesigned training platform that may eventually support specialized deployments beyond Earth.
Why it matters
Tesla's latest roadmap reveals a broader ambition than simply replacing one generation of vehicle processors with another. The company is pursuing a sequence of increasingly powerful inference accelerators while reviving Dojo as a separate training-hardware project. The SI labels put those efforts under a new vocabulary, but the technical changes are more significant than the name itself.
The 80-fold SI6 target is striking, yet it remains difficult to evaluate without confirmed HW4 specifications, supported numerical formats and power figures. The estimated TOPS range provides a useful indication of scale, not a guaranteed measure of real-world performance. Nvidia's already-shipping Rubin hardware also illustrates why delivery schedules matter as much as projected specifications.
Dojo 3 presents a different question. Its return suggests Tesla has not permanently abandoned custom training silicon, despite earlier statements about using Nvidia hardware across SpaceX and xAI infrastructure. The move toward chiplets and HBM indicates a substantial architectural rethink rather than a straightforward continuation of the original wafer-scale project.
The next meaningful milestones are the release of detailed SI5 specifications, confirmation of Samsung's exact SI6 manufacturing process, and more information about Dojo 3's packaging and space-oriented requirements. Tesla has not yet provided the performance figures, memory specifications or development schedule needed to judge the training accelerator's eventual capabilities.
Until those details emerge, the roadmap should be read as a statement of direction rather than proof of delivered performance. Tesla has outlined an ambitious hardware strategy, but its ability to turn the SI6 projections and Dojo 3's unconventional requirements into manufacturable products will determine how much of that ambition becomes reality.